Will return Fall 2023
To develop nanostructured 'chip scale' power and energy storage devices for use in miniaturized sensing, communication, and energy harvesting devices.
Due to ITAR and other access restrictions this project is limited to US citizens only.
Issues Involved or Addressed
This vertically integrated project (VIP) will create and characterize in operando chip-scale electrochemical double layer (ECDL) ‘supercapacitors’ that feature a functionalized pseudocapacitive architecture coupled with a tailored ionic-liquid-based electrolyte for rechargeable energy storage. Future years will integrate these devices into miniature sensors, energy harvesters, and IoT communication devices. Student researchers will fabricate supercapacitor electrodes using carbon nanotubes (CNTs) embedded within a silicon wafer. The CNTs will be further functionalized by both chemical and physical techniques, such as atomic layer deposition. The functionalized pseudocapacitive architecture will then be coupled with a tailored ionic-liquid-based electrolyte. The chip-scale devices will be packaged hermetically for incorporation as viable prototypes on mission architectures.
Methods and Technologies
Academic Majors of Interest
- Computing›OMSCS synchronous, case-by-case
- Engineering›Computer Engineering
- Engineering›Electrical Engineering
- Engineering›Materials Science and Engineering
- Engineering›Mechanical Engineering
Preferred Interests and Preparation
MSE, ECE, ME – Background/interest in materials and device design, synthesis, and characterization. Cleanroom and microscopy skills helpful but not required.
Meeting Schedule & Location
- Georgia Tech Research Institute