Secure Hardware

Back to List

2014 ~ Present | Cisco, Sandia National Labs and Georgia Tech Research Institute (GTRI).

Goals

To design digital hardware which is highly resistant to:

(i) reverse engineering and

(ii) attack by malicious hardware insertions (hardware Trojans).

 

Issues Involved or Addressed

Redesign of the logic structure of hardware to resist reverse engineering; hardware Trojan impact at run-time; design of block cyphers for encryption and decryption; duplication of digital logic in a non-obvious manner; mathematical proofs of algorithmic complexity.

Methods and Technologies

  • Digital Design
  • FPGA Programming
  • Encryption
  • VLSI Design
  • Digital Systems Test
  • Complexity Theory
  • Lattice Theory
  • Hardware/Software Codesign

Academic Majors of Interest

  • Computer Engineering
  • Computer Science
  • Electrical Engineering

Preferred Interests and Preparation

EE, CmpE – Background/interest in digital design, embedded systems, VLSI design and hardware/software codesign.

CmpE, CS – Background/interest in encryption, complexity theory and algorithms. Computer architecture would be helpful but is not required.

Meeting Schedule & Location

Time: 

4:30-5:20

Meeting Location: 

Klaus 2350

Meeting Day: 

Wednesday

Team Advisors

Dr. Vincent Mooney
  • ECE

Partner(s) and Sponsor(s)

Cisco, Sandia National Labs and Georgia Tech Research Institute (GTRI).

Course or Section Number

VPM