GOALS: To design digital hardware which is highly resistant to (i) reverse engineering and (ii) attack by malicious hardware insertions (hardware Trojans).
METHODS & TECHNOLOGIES: Digital design, FPGA programming, encryption, VLSI design, digital systems test, complexity theory, lattice theory and hardware/software codesign.
RESEARCH/DESIGN ISSUES: Redesign of the logic structure of hardware to resist reverse engineering; hardware Trojan impact at run-time; design of block cyphers for encryption and decryption; duplication of digital logic in a non-obvious manner; mathematical proofs of algorithmic complexity.
MEETING TIME: Wed, 4:30-5:20
ADVISORS: Vincent Mooney (ECE)
PARTNERS & SPONSORS: Cisco, Sandia National Labs and Georgia Tech Research Institute (GTRI).
MAJORS, PREPARATION AND INTERESTS:
EE, CmpE – Background/interest in digital design, embedded systems, VLSI design and hardware/software codesign.
CmpE, CS – Background/interest in encryption, complexity theory and algorithms. Computer architecture would be helpful but is not required.
CONTACT: Prof. Vincent Mooney, 404-385-0437, email@example.com
AWARDS: Won second place in 2018 VIP Innovation Competition's Systems Track