Chip Scale Power & Energy (NOFORN)
** Due to ITAR and other access restrictions this project is limited to US citizens only**
GOALS: To develop nanostructured 'chip scale' power & energy storage devices for use in miniaturized sensing, communication, and energy harvesting devices.
METHODS & TECHNOLOGIES: Cleanroom microfabrication; nanomaterial synthesis; electron microscopy; in situ raman spectroscopy; electrical design.
RESEARCH/DESIGN ISSUES: This vertically integrated project (VIP) will create and characterize in operando chip-scale electrochemical double layer (ECDL) ‘supercapacitors’ that feature a functionalized pseudocapacitive architecture coupled with a tailored ionic-liquid-based electrolyte for rechargeable energy storage. Future years will integrate these devices into miniature sensors, energy harvesters, and IoT communication devices. Student researchers will fabricate supercapacitor electrodes using carbon nanotubes (CNTs) embedded within a silicon wafer. The CNTs will be further functionalized by both chemical and physical techniques, such as atomic layer deposition. The functionalized pseudocapacitive architecture will then be coupled with a tailored ionic-liquid-based electrolyte. The chip-scale devices will be packaged hermetically for incorporation as viable prototypes on mission architectures.
MEETING TIME: Thurs, 9:30 - 10:20
ADVISORS: Jud Ready (GTRI), Meilin Liu (MSE)
PARTNERS & SPONSORS: NASA-JPL; Duracell; SOCOM
MAJORS, PREPARATION AND INTERESTS: MSE, ECE, ME – Background/interest in materials and device design, synthesis, and characterization. Cleanroom and microscopy skills helpful but not required.
CONTACT: Dr. Jud Ready, firstname.lastname@example.org; 404-407-6036